TY - GEN
T1 - Reliable and efficient system-on-chip design
AU - Shanbhag, Naresh R.
N1 - Funding Information:
Naresh R. P ower dissipation is a concern in both The design and electronic design automation Shanbhag microprocessors and communication sys-(EDA) communities must work closely with the University of Illinois tems. High power dissipation increases process engineering community to address these at Urbana- the substrate temperature of integrated problems. Researchers in academia and industry Champaign circuits, which increases leakage currents, have taken major steps in this direction by estab-reduces performance and battery life for mobile lishing the multiple-university Gigascale Silicon applications, and adversely impacts material relia-Research Center and the Center for Circuit & bility. System Solutions. Both centers, funded through the Supply noise (bounce and IR drops), leakage, and Microelectronics Advanced Research Corporation interconnect noise (coupling) impact signal phase (MARCO) by the Semiconductor Industry and amplitude, while process variations result in Association and the Defense Advanced Research uncertainty and create a mismatch between signal Projects Agency, initiated reliability research thrusts paths. Both noise and process variations impact reli-beginning in 2003. ability, causing logic errors that can result in system Microprocessor designs must achieve high per-failure. formance and energy efficiency in the presence of To increase processor performance, the micro-noise. A communication-theoretic paradigm1 for reli-processor industry is driving the scaling of feature able and efficient system-on-chip (SoC) design views sizes into the deep-submicron (DSM) and sub-100-integrated microsystems as miniature communica-nanometer regime. Unfortunately, power/perfor-tion networks operating in the presence of noise. First mance-enhancing design techniques only aggravate proposed in 1997, this paradigm has evolved into the reliability problem. For example, the popular two distinct but related areas of research: supply voltage scaling technique reduces power, but it does so at the expense of noise immunity. Although researchers have developed complex power management systems and expensive packaging schemes, the recent emergence of noise and the dramatic increase in process variations have raised
Funding Information:
filter blocks, resulting in very high overhead. In transmission2 used Hamming and Reed-Muller such a case, the assumption of an error-free error-codes along with a reverse retransmission request control block can be relaxed. channel to reduce signaling levels in the frequently used forward channel. Simulations demonstrated NOISE-TOLERANT BUS TRANSMISSION a three-to fourfold power savings, but again this Buses are key SoC components. Coupling work does not address coupling. Use of error-detec-between adjacent wires, supply bounce at the tion and retransmission was recently proposed for receiver, and other sources can cause noise in buses. reliable communications in networks-on-a-chip.14 Energy consumption in buses occurs mainly due to A remaining challenge is to develop noise-transitions on bus lines, including charging and dis-tolerant bus transmission codes that jointly address charging the self and coupling capacitances. coupling, self-capacitance, and noise. Early bus power-reduction techniques ignored coupling, focusing instead on reducing transition activity in individual bit lines. As Figure 8a shows, he semiconductor industry faces numerous a bus-coding framework13 based on source cod-challenges in developing reliable, energy-ing—for example, video compression employed T efficient SoC designs that are on a par with in multimedia communication networks—has modern communications systems. Researchers three key elements. The predictor F can be an iden-must explore the tradeoffs between reliability and tity or an increment function; the differentiator f1 energy efficiency at the device, circuit, architectural, can be an XOR or a subtractor; and the mapper f2 algorithmic, and system levels to develop a relia-can employ a probability-based mapping, value-bility-energy “knob” that can be synergistically based mapping, inversion, or identity function. tuned to meet these requirements at each level of Assigning different functionalities to F, f1, and f2 the design hierarchy. Elegant and practical solu-results in a family of coding schemes demonstrat-tions will require the application of coding and ing this framework’s power. For example, the fol-communication-theoretic techniques to the design lowing assignment can derive the well-known of SoC components. In addition, researchers must bus-invert scheme from this framework: F = identity, develop statistical approaches to design and verifi-f1 = XOR, and f2 = inversion. Another useful coding cation as well as statistical performance metrics. ■ scheme for address buses is INC-XOR, obtained by the following assignment: F = increment, f1 = XOR, and f2 = identity. Acknowledgments These and other similar techniques that focus on This work was supported by the MARCO-spon-reducing transition activity in individual bus lines sored Gigascale Silicon Research Center and ignore the problem of coupling found in DSM National Science Foundation grants CCR-000987 processes. Recent work uses coding to minimize and CCR-0095929. I also thank Krisnamurthy transitions on adjacent bus lines, thereby reducing Soumyanath, Ram Krishnamurthy, Tanay Karnik, delay. However, none of these techniques address and Shekhar Borkar at Intel as well as current and the noise problem. former graduate students Sumant Ramprasad, Raj As Figure 8b shows, the first work addressing Hegde, Lei Wang, Byonghyo Shim, and Ganesh noise and energy efficiency in high-speed SoC bus Balamurugan for their contributions.
PY - 2004/3
Y1 - 2004/3
N2 - The semiconductor industry faces numerous challenges in developing reliable, energy-efficent SoC designs that are on a par with modern communications systems. Researchers must explore the tradeoffs between reliability and energy efficiency at the device, circuit, architectural, algorithmic, and system levels to develop a reliability-energy "knob" that can be synergistically tuned to meet such requirements at each level of the design hierarchy. As such, elegant and practical solutions will require the application of coding and communication-theoretic techniques to the design of SoC components.
AB - The semiconductor industry faces numerous challenges in developing reliable, energy-efficent SoC designs that are on a par with modern communications systems. Researchers must explore the tradeoffs between reliability and energy efficiency at the device, circuit, architectural, algorithmic, and system levels to develop a reliability-energy "knob" that can be synergistically tuned to meet such requirements at each level of the design hierarchy. As such, elegant and practical solutions will require the application of coding and communication-theoretic techniques to the design of SoC components.
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U2 - 10.1109/MC.2004.1274003
DO - 10.1109/MC.2004.1274003
M3 - Article
AN - SCOPUS:1842582494
VL - 37
SP - 42
EP - 50
JO - Computer
JF - Computer
SN - 0018-9162
ER -