Register multimapping: A technique for reducing register bank conflicts in processors with large register files

Nam Duong, Rakesh Kumar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we investigate Register Multimapping as a technique to reduce register bank conflicts for processors with large register files, but relatively slow clock speeds. Register multimapping involves mapping an architectural register to multiple physical registers belonging to different banks. Reads can proceed using any of the physical registers, thereby minimizing read bank conflicts. Write conflicts can be minimized by allowing delayed allocation of physical registers [5]. Our experiments show that register multimapping can result in performance improvements up to 15% (10% on average) over baseline processors that are port-constrained. Improvements are up to 13% (5.5% on average) over port-constrained processorsthat support delayed allocation of registers.

Original languageEnglish (US)
Title of host publication2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009
Pages50-53
Number of pages4
DOIs
StatePublished - 2009
Event2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009 - San Francisco, CA, United States
Duration: Jul 27 2009Jul 28 2009

Publication series

Name2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009

Other

Other2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009
Country/TerritoryUnited States
CitySan Francisco, CA
Period7/27/097/28/09

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture

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