Reducing the scheduling critical cycle using wakeup prediction

Todd E. Ehrhart, Sanjay Jeram Patel

Research output: Contribution to journalConference articlepeer-review


For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a cycle of logic involving wakeup and select. However, the time a static instruction spends waiting for wakeup shows little dynamic variance. This idea is used to build a machine where wakeup times are predicted, and instructions executed too early are replayed. This form of self-scheduling reduces the critical cycle by eliminating the wakeup logic at the expense of additional replays. However, replays and other pipeline effects affect the cost of misprediction. To solve this, an allowance is added to the predicted wakeup time to decrease the probability of a replay. This allowance may be associated with individual instructions or the global state, and is dynamically adjusted by a gradient-descent minimum-searching technique. When processor load is low, prediction may be more aggressive - increasing the chance of replays, but increasing performance, so the aggressiveness of the predictor is dynamically adjusted using processor load as a feedback parameter.

Original languageEnglish (US)
Pages (from-to)222-231
Number of pages10
JournalIEEE High-Performance Computer Architecture Symposium Proceedings
StatePublished - 2004
EventProceedings - 10th International Symposium on High Performance Computer Architecture - Madrid, Spain
Duration: Feb 14 2004Feb 18 2004

ASJC Scopus subject areas

  • Hardware and Architecture


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