Reducing Register Ports Using Delayed Write-Back Queues and Operand Pre-Fetch

Keyphrases

• Microprocessor 100%
• Writing Back 100%
• Operand 100%
• Access Time 100%
• Prefetching 100%
• Register File 100%
• High Performance 50%
• Global Interconnect 50%
• Clock Frequency 50%
• Memory Structure 50%
• Small Files 50%
• Auxiliary Structure 50%
• Area Saving 50%
• Energy Access 50%
• Time-area 50%
• Auxiliary Memory 50%

Engineering

• Access Time 100%
• Register File 100%
• Port Register 100%
• Interconnects 50%
• Microprocessor Chips 50%
• Clock Speed 50%
• Critical Path 50%
• Microprocessor 50%

Computer Science

• Prefetch 100%
• Memory Structure 100%
• Critical Path 100%
• Microprocessor Chips 100%
• Microprocessor 100%