Reducing Register Ports Using Delayed Write-Back Queues and Operand Pre-Fetch

Nam Sung Kim, Trevor Mudge

Research output: Contribution to conferencePaperpeer-review

Abstract

In high-performance wide-issue microprocessors the access time, energy and area of the register file are often critical to overall performance. This is because these parameters grow superlinearly as read and write ports are added to support wide-issue. This paper presents techniques to reduce the number of ports of a register file intended for a wide-issue microprocessor without noticeably impacting its IPC. Our results show that it is possible to replace the 16 read/8 write port file of an eight-issue processor with an 8 read/8 write port file so that the impact on IPC is insignificant. This is accomplished with the addition of some small auxiliary memory structures. Furthermore, the access time of the smaller file plus the auxiliary structures is such that if it were the critical path a 45-50% increase in clock speed would be possible. Finally, there is an energy per access savings of about 20% and an area savings of 40%, which has the potential for further savings by shortening global interconnect in the layout. An extension to the scheme that reduces the number of write ports from 8 to 6 is also presented. It suffers modest penalty in terms of IPC, but shows further reduction in energy and area. Depending on implementation characteristics it could yield a further increase in performance.

Original languageEnglish (US)
Pages172-182
Number of pages11
DOIs
StatePublished - 2003
Externally publishedYes
Event2003 International Conference on Supercomputing - San Francisco, CA, United States
Duration: Jun 23 2003Jun 26 2003

Other

Other2003 International Conference on Supercomputing
CountryUnited States
CitySan Francisco, CA
Period6/23/036/26/03

Keywords

  • Instruction Level Parallelism
  • Low Power
  • Out-of-order Processor
  • Register File
  • Write Queue

ASJC Scopus subject areas

  • Computer Science(all)

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