Reducing power by optimizing the necessary precision/range of floating-point arithmetic

Jonathan Ying Fai Tong, David Nagle, Rob A. Rutenbar

Research output: Contribution to journalArticle

Abstract

Low-power systems often find the power cost of floating-point (FP) hardware prohibitively expensive. This paper explores ways of reducing FP power consumption by minimizing the bitwidth representation of FP data. Analysis of several FP programs that manipulate low-resolution human sensory data shows that these programs suffer no loss of accuracy even with a significant reduction in bitwidth. Most FP programs in our benchmark suite maintain the same output even when the mantissa bitwidth is reduced by half. This FP bitwidth reduction can deliver a significant power saving through the use of a variable bitwidth FP unit. Our results show that up to 66% reduction in multiplier energy/operation can be achieved in the FP unit by this bitwidth reduction technique without sacrificing any program accuracy.

Original languageEnglish (US)
Pages (from-to)273-286
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume8
Issue number3
DOIs
StatePublished - Dec 3 2000

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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