As semiconductor feature sizes and pitches shrink to ever-decreasing dimensions, Line Edge Roughness (LER) becomes and increasing important problem 1. The LER is transferred from the photoresist to the substrate through the subsequent processing steps, causing variations in, eg, gate length. This leads to mismatch in device performance and leakage 2. Thus, an efficient and cost effective way to reduce the LER in the semiconductor photoresist is needed in order to keep the imperfections from affecting processing steps further down the line. At the CPMI a new technique to reduce LER from patterened photoresist has been developed in conjunction with INTEL.Results obtained using our technique showed significant LER reduction from 6.9±0.47 nm to 3.9±0.61 nm for 45 nm lines and spaces. Recent results on 40 nm lines and spaces showed significant LER reduction from 5.9±0.50 nm to 4.1±0.63nm. LER reduction results on 40 nm lines and spaces reveal the fact that our technique is superior to other available techniques such as etching, vapor smoothing, hardbake, ozonation and rinse 3.