Reconfigurable heterogeneous integration using stackable chips with embedded artificial intelligence

Chanyeol Choi, Hyunseok Kim, Ji Hoon Kang, Min Kyu Song, Hanwool Yeon, Celesta S. Chang, Jun Min Suh, Jiho Shin, Kuangye Lu, Bo In Park, Yeongin Kim, Han Eol Lee, Doyoon Lee, Jaeyong Lee, Ikbeom Jang, Subeen Pang, Kanghyun Ryu, Sang Hoon Bae, Yifan Nie, Hyun S. KumMin Chul Park, Suyoun Lee, Hyung Jun Kim, Huaqiang Wu, Peng Lin, Jeehwan Kim

Research output: Contribution to journalArticlepeer-review

Abstract

Artificial intelligence applications have changed the landscape of computer design, driving a search for hardware architecture that can efficiently process large amounts of data. Three-dimensional heterogeneous integration with advanced packaging technologies could be used to improve data bandwidth among sensors, memory and processors. However, such systems are limited by a lack of hardware reconfigurability and the use of conventional von Neumann architectures. Here we report stackable hetero-integrated chips that use optoelectronic device arrays for chip-to-chip communication and neuromorphic cores based on memristor crossbar arrays for highly parallel data processing. With this approach, we create a system with stackable and replaceable chips that can directly classify information from a light-based image source. We also modify this system by inserting a preprogrammed neuromorphic denoising layer that improves the classification performance in a noisy environment. Our reconfigurable three-dimensional hetero-integrated technology can be used to vertically stack a diverse range of functional layers and could provide energy-efficient sensor computing systems for edge computing applications.

Original languageEnglish (US)
Pages (from-to)386-393
Number of pages8
JournalNature Electronics
Volume5
Issue number6
DOIs
StatePublished - Jun 2022
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Instrumentation
  • Electrical and Electronic Engineering

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