Reconfigurable caches and their application to media processing

Parthasarathy Ranganathan, Sarita Adve, Norman P. Jouppi

Research output: Contribution to journalConference articlepeer-review


High performance general-purpose processors are increasingly being used for a variety of application domains - scientific, engineering, databases, and more recently, media processing. It is therefore important to ensure that architectural features that use a significant fraction of the on-chip transistors are applicable across these different domains. For example, current processor designs often devote the largest fraction of on-chip transistors (up to 80%) to caches. Many workloads, however, do not make effective use of large caches; e.g., media processing workloads which often have streaming data access patterns and large working sets. This paper proposes a new reconfigurable cache design. This design enables the cache SRAM arrays to be dynamically divided into multiple partitions that can be used for different processor activities. These activities can benefit applications that would otherwise not use the storage allocated to large conventional caches. Our design involves relatively few modifications to conventional cache design, and analysis using a modification of the CACTI analytical model shows a small impact on cache access time. We evaluate one representative use of reconfigurable caches - instruction reuse for media processing. We find this use gives IPC improvements ranging from 1.04X to 1.20X in simulation across eight media processing benchmarks.

Original languageEnglish (US)
Pages (from-to)214-224
Number of pages11
JournalConference Proceedings - Annual International Symposium on Computer Architecture, ISCA
StatePublished - 2000
Externally publishedYes
EventISCA-27: The 27th Annual International Symposium on Computer Architecture - Vancouver, BC, Can
Duration: Jun 10 2000Jun 14 2000

ASJC Scopus subject areas

  • Hardware and Architecture


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