@inproceedings{5477be5bd6e0411f95f3d950dec3f03a,
title = "Reconciling Predictability and Coherent Caching",
abstract = "Real-time systems are required to respond to their physical environment within predictable time. While multi-core platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability. For parallel applications with data shared across multiple cores, overhead to maintain data coherence is a major cause of execution time variability. This source of variability can be eliminated by application level control for limiting data caching at different levels of the cache hierarchy. This removes the requirement of explicit coherence machinery for selected data. We show that such control can reduce the worst case write request latency on shared data by 52%. Benchmark evaluations show that proposed technique has a minimal impact on average performance.",
keywords = "cache coherence, hardware/software co-design, memory contention, worst-case execution time",
author = "Ayoosh Bansal and Jayati Singh and Yifan Hao and Wen, {Jen Yang} and Renato Mancuso and Marco Caccamo",
note = "Funding Information: ACKNOWLEDGMENT The material presented in this paper is based upon work supported by the Office of Naval Research (ONR) under grant number N00014-17-1-2783 and by the National Science Foundation (NSF) under grant numbers CNS 1646383, CNS 1932529 and CNS 18-15891. M. Caccamo was also supported Publisher Copyright: {\textcopyright} 2020 IEEE.; 9th Mediterranean Conference on Embedded Computing, MECO 2020 ; Conference date: 08-06-2020 Through 11-06-2020",
year = "2020",
month = jun,
doi = "10.1109/MECO49872.2020.9134262",
language = "English (US)",
series = "2020 9th Mediterranean Conference on Embedded Computing, MECO 2020",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2020 9th Mediterranean Conference on Embedded Computing, MECO 2020",
address = "United States",
}