RECO-ASCON: Reconfigurable ASCON hash functions for IoT applications

The need for reconfigurable lightweight cryptographic processors with low power consumption for securing the Internet of Things (IoT) with adaptive functionalities is getting attracted due to security properties, such as data fidelity, provenance, and privacy concerns. This paper presents RECO-ASCON, a reconfigurable security processor that supports both cryptographic Hash and Hasha ASCON algorithms. The proposed design is implemented in Chisel hardware construction language, an open-source hardware library. It has been evaluated in various hardware platforms such as FPGAs, embedded systems and ASICs with various technology nodes and design flows. In the PYNQ-Z1 board, RECO-ASCON can be mapped to five processors in total with a Micro-Blaze soft-core processor for streaming data to all of them while running at 200 MHz without producing any timing violations. Moreover, mapping the proposed RECO-ASCON processor on the Nexsys4-DDR Xilinx Kit (ARTIX-7 chip) would cost ∼ two times fewer resources and run 1.25 × faster than the existing implementation of just one of the ASCON hash functions on the same family of the chip. We implement the proposed processor in 28 nm industry technology with commercial design flow, it achieves a maximum frequency of 1.12 GHz while achieving highest energy efficiency compared to the state-of-the-art implementations. The total area is only 9170.82um² in 28 nm. To further evaluate the design, we also implement it with all open-source design tools and process technology libraries in 45 nm, it achieves 1 GHz maximum frequency and consumes only 18225um² in 45 nm. Overall, the proposed reconfigurable processor is compact and more energy efficient, making it a perfect candidate to be deployed in wide range of IoT systems.