Recent advances in memory consistency models for hardware shared memory systems

Sarita V. Adve, Vijay S. Pai, Parthasarathy Ranganathan

Research output: Contribution to journalArticlepeer-review

Abstract

The memory consistency model of a shared memory system determines the order in which memory operations will appear to execute to the programmer. The memory consistency model for a system typically involves a tradeoff behvcen performance and programmability. This paper provides an ovemew of recent advances in hardware optimizations, compiler optimizations, and programming environments relevant to memory consistency models of hardware distributed shared memory systems. We discuss recent hardware and compiler optimizations that exploit the observation that it is sufficient to only appear as if the ordering rules of the consistency model are obeyed. These optimizations substantially improve the performance of the strictest consistency model, making it more attractive for its programmability. Recent concurrent programming languages and environments, on the other hand, support more relaxed consistency models. We discuss several such environments, including POS1X threads, Java, and OpenMP.

Original languageEnglish (US)
Pages (from-to)445-455
Number of pages11
JournalProceedings of the IEEE
Volume87
Issue number3
DOIs
StatePublished - 1999
Externally publishedYes

Keywords

  • Hardware shared memory
  • Instruction-level parallelism
  • Memory consistency
  • Performance
  • Programmability

ASJC Scopus subject areas

  • Computer Science(all)
  • Electrical and Electronic Engineering

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