Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS

Ganesh Balamurugan, James Jaussi, David R. Johnson, Bryan Casper, Aaron Martin, Joe Kennedy, Randy Mooney, Naresh R Shanbhag

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper describes a 0.13μm CMOS, SGbps I/O receiver that uses on-die circuits for receiver adaptation and system characterization. On-die adaptive control is used to tune a 4-tap receive-side analog equalizer, cancel receiver offsets, and determine optimal sampling phase. Adaptive equalization improves data rates by 1.3×-2× over 2"-40" FR4 channels. Noise-margin degradation due to statistical variation in adapted coefficients and offsets is less than 3% of the signal swing. On-die circuits are also used to characterize link performance, channel response, and receiver circuits.

Original languageEnglish (US)
Pages356-359
Number of pages4
StatePublished - Sep 29 2004
Event2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States
Duration: Jun 17 2004Jun 19 2004

Other

Other2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
CountryUnited States
CityHonolulu, HI
Period6/17/046/19/04

Keywords

  • Adaptation
  • Backplane
  • Equalization
  • FR4
  • I/O
  • Offset cancellation
  • Source-synchronous signaling

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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