Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS

Ganesh Balamurugan; James Jaussi; David R. Johnson; Bryan Casper; Aaron Martin; Joe Kennedy; Randy Mooney; Naresh Shanbhag

Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS

Ganesh Balamurugan, James Jaussi, David R. Johnson, Bryan Casper, Aaron Martin, Joe Kennedy, Randy Mooney, Naresh Shanbhag

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper describes a 0.13μm CMOS, SGbps I/O receiver that uses on-die circuits for receiver adaptation and system characterization. On-die adaptive control is used to tune a 4-tap receive-side analog equalizer, cancel receiver offsets, and determine optimal sampling phase. Adaptive equalization improves data rates by 1.3×-2× over 2"-40" FR4 channels. Noise-margin degradation due to statistical variation in adapted coefficients and offsets is less than 3% of the signal swing. On-die circuits are also used to characterize link performance, channel response, and receiver circuits.

Original language	English (US)
Pages	356-359
Number of pages	4
State	Published - 2004
Event	2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States Duration: Jun 17 2004 → Jun 19 2004

Other

Other	2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
Country/Territory	United States
City	Honolulu, HI
Period	6/17/04 → 6/19/04

Keywords

Adaptation
Backplane
Equalization
FR4
I/O
Offset cancellation
Source-synchronous signaling

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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Balamurugan, G., Jaussi, J., Johnson, D. R., Casper, B., Martin, A., Kennedy, J., Mooney, R., & Shanbhag, N. (2004). Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS. 356-359. Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States.

Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS. / Balamurugan, Ganesh; Jaussi, James; Johnson, David R. et al.
2004. 356-359 Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States.

Research output: Contribution to conference › Paper › peer-review

Balamurugan, G, Jaussi, J, Johnson, DR, Casper, B, Martin, A, Kennedy, J, Mooney, R & Shanbhag, N 2004, 'Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS', Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States, 6/17/04 - 6/19/04 pp. 356-359.

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abstract = "This paper describes a 0.13μm CMOS, SGbps I/O receiver that uses on-die circuits for receiver adaptation and system characterization. On-die adaptive control is used to tune a 4-tap receive-side analog equalizer, cancel receiver offsets, and determine optimal sampling phase. Adaptive equalization improves data rates by 1.3×-2× over 2{"}-40{"} FR4 channels. Noise-margin degradation due to statistical variation in adapted coefficients and offsets is less than 3% of the signal swing. On-die circuits are also used to characterize link performance, channel response, and receiver circuits.",

keywords = "Adaptation, Backplane, Equalization, FR4, I/O, Offset cancellation, Source-synchronous signaling",

author = "Ganesh Balamurugan and James Jaussi and Johnson, {David R.} and Bryan Casper and Aaron Martin and Joe Kennedy and Randy Mooney and Naresh Shanbhag",

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AU - Balamurugan, Ganesh

AU - Jaussi, James

AU - Johnson, David R.

AU - Casper, Bryan

AU - Martin, Aaron

AU - Kennedy, Joe

AU - Mooney, Randy

AU - Shanbhag, Naresh

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N2 - This paper describes a 0.13μm CMOS, SGbps I/O receiver that uses on-die circuits for receiver adaptation and system characterization. On-die adaptive control is used to tune a 4-tap receive-side analog equalizer, cancel receiver offsets, and determine optimal sampling phase. Adaptive equalization improves data rates by 1.3×-2× over 2"-40" FR4 channels. Noise-margin degradation due to statistical variation in adapted coefficients and offsets is less than 3% of the signal swing. On-die circuits are also used to characterize link performance, channel response, and receiver circuits.

AB - This paper describes a 0.13μm CMOS, SGbps I/O receiver that uses on-die circuits for receiver adaptation and system characterization. On-die adaptive control is used to tune a 4-tap receive-side analog equalizer, cancel receiver offsets, and determine optimal sampling phase. Adaptive equalization improves data rates by 1.3×-2× over 2"-40" FR4 channels. Noise-margin degradation due to statistical variation in adapted coefficients and offsets is less than 3% of the signal swing. On-die circuits are also used to characterize link performance, channel response, and receiver circuits.

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KW - Backplane

KW - Equalization

KW - FR4

KW - I/O

KW - Offset cancellation

KW - Source-synchronous signaling

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Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS

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