Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS

Ganesh Balamurugan, James Jaussi, David R. Johnson, Bryan Casper, Aaron Martin, Joe Kennedy, Randy Mooney, Naresh R Shanbhag

Research output: Contribution to conferencePaper

Abstract

This paper describes a 0.13μm CMOS, SGbps I/O receiver that uses on-die circuits for receiver adaptation and system characterization. On-die adaptive control is used to tune a 4-tap receive-side analog equalizer, cancel receiver offsets, and determine optimal sampling phase. Adaptive equalization improves data rates by 1.3×-2× over 2"-40" FR4 channels. Noise-margin degradation due to statistical variation in adapted coefficients and offsets is less than 3% of the signal swing. On-die circuits are also used to characterize link performance, channel response, and receiver circuits.

Original languageEnglish (US)
Pages356-359
Number of pages4
StatePublished - Sep 29 2004
Event2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States
Duration: Jun 17 2004Jun 19 2004

Other

Other2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
CountryUnited States
CityHonolulu, HI
Period6/17/046/19/04

Fingerprint

Networks (circuits)
Equalizers
Sampling
Degradation

Keywords

  • Adaptation
  • Backplane
  • Equalization
  • FR4
  • I/O
  • Offset cancellation
  • Source-synchronous signaling

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Balamurugan, G., Jaussi, J., Johnson, D. R., Casper, B., Martin, A., Kennedy, J., ... Shanbhag, N. R. (2004). Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS. 356-359. Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States.

Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS. / Balamurugan, Ganesh; Jaussi, James; Johnson, David R.; Casper, Bryan; Martin, Aaron; Kennedy, Joe; Mooney, Randy; Shanbhag, Naresh R.

2004. 356-359 Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States.

Research output: Contribution to conferencePaper

Balamurugan, G, Jaussi, J, Johnson, DR, Casper, B, Martin, A, Kennedy, J, Mooney, R & Shanbhag, NR 2004, 'Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS' Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States, 6/17/04 - 6/19/04, pp. 356-359.
Balamurugan G, Jaussi J, Johnson DR, Casper B, Martin A, Kennedy J et al. Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS. 2004. Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States.
Balamurugan, Ganesh ; Jaussi, James ; Johnson, David R. ; Casper, Bryan ; Martin, Aaron ; Kennedy, Joe ; Mooney, Randy ; Shanbhag, Naresh R. / Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 μm CMOS. Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States.4 p.
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