Abstract
A simple but efficient architecture for building multiprocessors is to connect several processors to a common backplane bus. The backplane acts as a shared resource in this architecture and contention for its use by different bus modules must be resolved. In a real-time system, this backplane must also provide scheduling support such that the timing behavior of the resulting system is analyzable. In addition, the support primitives for real-time scheduling on a backplane bus must also be constrained by the economic considerations associated with a bus standard that is intended to support both time sharing and real-time applications. The authors review the design considerations to support real-time systems in the IEEE Futurebus+ backplane specification and describe how this backplane can be used to satisfy timing constraints in priority-driven real-time systems.
Original language | English (US) |
---|---|
Title of host publication | 90 Real-Time Syst. Symp. |
Publisher | Publ by IEEE |
Pages | 331-340 |
Number of pages | 10 |
ISBN (Print) | 0818621125 |
State | Published - Oct 1991 |
Externally published | Yes |
Event | Proceedings of the 11th Real-Time Systems Symposium - Lake Buena Vista, FL, USA Duration: Dec 5 1990 → Dec 7 1990 |
Other
Other | Proceedings of the 11th Real-Time Systems Symposium |
---|---|
City | Lake Buena Vista, FL, USA |
Period | 12/5/90 → 12/7/90 |
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Computer Networks and Communications