Real-time communication for multicore systems with multi-domain ring buses

Bach D. Bui, Rodolfo Pellizzoni, Deepti K. Chivukula, Marco Caccamo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We address the problem of scheduling real-time data transactions on a multicore processor bus. In particular, to increase system predictability and tighten WCET estimation, we propose to employ a software-controllable Multi-Domain Ring Bus (MDRB) architecture. The problem of scheduling periodic real-time transactions on MDRB is challenging because the bus allows multiple non-overlapping transactions to be executed concurrently, and because the degree of concurrency depends on the topology of the bus and of executed transactions. We propose a practical abstraction mechanism for the scheduling problem together with two novel scheduling algorithms. The first algorithm is optimal for transaction sets under restrictive assumptions while the second one induces a competitive sufficient schedulable utilization bound for more general transaction sets.

Original languageEnglish (US)
Title of host publicationProceedings - 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2010
Pages23-32
Number of pages10
DOIs
StatePublished - Nov 24 2010
Event16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2010 - Macau, China
Duration: Aug 23 2010Aug 25 2010

Publication series

NameProceedings - 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2010

Other

Other16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2010
Country/TerritoryChina
CityMacau
Period8/23/108/25/10

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications
  • Hardware and Architecture

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