Reachability analysis of nonlinear analog circuits through iterative reachable set reduction

Seyed Nematollah Ahmadyan, Shobha Vasudevan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a methodology for reachability analysis of nonlinear analog circuits to verify safety properties. Our iterative reachable set reduction algorithm initially considers the entire state space as reachable. Our algorithm iteratively determines which regions in the state space are unreachable and removes those unreachable regions from the over approximated reachable set. We use the State Partitioning Tree (SPT) algorithm to recursively partition the reachable set into convex polytopes. We determine the reachability of adjacent neighbor polytopes by analyzing the direction of state space trajectories at the common faces between two adjacent polytopes. We model the direction of the trajectories as a reachability decision function that we solve using a sound root counting method. We are faithful to the nonlinearities of the system. We demonstrate the memory efficiency of our algorithm through computation of the reachable set of Van der Pol oscillation circuit.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2013
Pages1436-1441
Number of pages6
StatePublished - 2013
Event16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 - Grenoble, France
Duration: Mar 18 2013Mar 22 2013

Other

Other16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
CountryFrance
CityGrenoble
Period3/18/133/22/13

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Ahmadyan, S. N., & Vasudevan, S. (2013). Reachability analysis of nonlinear analog circuits through iterative reachable set reduction. In Proceedings - Design, Automation and Test in Europe, DATE 2013 (pp. 1436-1441). [6513739]