ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor With Compiler-Architecture Co-Design

Keyphrases

• Parallelization 100%
• Reconfigurable 100%
• Design Scheme 100%
• Array Processor 100%
• Compiler Architecture 100%
• On-chip Memory 66%
• Data Reuse 66%
• Compute-intensive 66%
• Array Architecture 33%
• Design Requirements 33%
• Precise Data 33%
• Hardware Accelerator 33%
• Data Management 33%
• Data Access 33%
• Reconfigurable Computing 33%
• Whole Systems 33%
• Massive Data 33%
• Compiler 33%
• Data Locality 33%
• FPGA Platform 33%
• Software Flexibility 33%
• Memory Bound 33%
• Reconfigurable Array 33%
• High Utilization 33%
• Hardware Resources 33%
• Hardware Parallelism 33%
• Deep Neural Network 33%
• Embedded FPGA 33%
• U-Net 33%
• Deep Learning Algorithm 33%
• Deep Learning Workloads 33%
• MobileNet 33%
• Deep Learning Processor 33%
• Systemic Optimization 33%
• Domain-specific Compiler 33%

Computer Science

• Participatory Design 100%
• Array Processor 100%
• Parallelism 75%
• Deep Learning 75%
• Data Reuse 50%
• Experimental Result 25%
• hardware acceleration 25%
• Design Requirement 25%
• Data Access 25%
• reconfigurable computing 25%
• Data Management 25%
• Data Locality 25%
• Memory Bound 25%
• Hardware Resource 25%
• Hardware Parallelism 25%
• Deep Neural Network 25%
• Bidirectional Encoder Representations From Transformers 25%
• Residual Neural Network 25%