Razor: Circuit-level correction of timing errors for low-power operation

Dan Ernst; Shidhartha Das; Seokwoo Lee; David Blaauw; Todd Austin; Trevor Mudge; Nam Sung Kim; Krisztiéan Flautner

doi:10.1109/MM.2004.85

Razor: Circuit-level correction of timing errors for low-power operation

Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd Austin, Trevor Mudge, Nam Sung Kim, Krisztiéan Flautner

Research output: Contribution to journal › Article › peer-review

Abstract

Dynamic voltage scalling is one of the more effective and widely used methods for power-aware computing. Here is a DVS approach that uses dynamic detection and correction of circuit timing errors to tune processor supply voltage and eliminate the need for voltage margins.

Original language	English (US)
Pages (from-to)	10-20
Number of pages	11
Journal	IEEE Micro
Volume	24
Issue number	6
DOIs	https://doi.org/10.1109/MM.2004.85
State	Published - Nov 2004
Externally published	Yes

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MM.2004.85

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@article{2051adaa7def457ca9797892958d6664,

title = "Razor: Circuit-level correction of timing errors for low-power operation",

abstract = "Dynamic voltage scalling is one of the more effective and widely used methods for power-aware computing. Here is a DVS approach that uses dynamic detection and correction of circuit timing errors to tune processor supply voltage and eliminate the need for voltage margins.",

author = "Dan Ernst and Shidhartha Das and Seokwoo Lee and David Blaauw and Todd Austin and Trevor Mudge and Kim, {Nam Sung} and Kriszti{\'e}an Flautner",

year = "2004",

month = nov,

doi = "10.1109/MM.2004.85",

language = "English (US)",

volume = "24",

pages = "10--20",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "6",

}

TY - JOUR

T1 - Razor

T2 - Circuit-level correction of timing errors for low-power operation

AU - Ernst, Dan

AU - Das, Shidhartha

AU - Lee, Seokwoo

AU - Blaauw, David

AU - Austin, Todd

AU - Mudge, Trevor

AU - Kim, Nam Sung

AU - Flautner, Krisztiéan

PY - 2004/11

Y1 - 2004/11

N2 - Dynamic voltage scalling is one of the more effective and widely used methods for power-aware computing. Here is a DVS approach that uses dynamic detection and correction of circuit timing errors to tune processor supply voltage and eliminate the need for voltage margins.

AB - Dynamic voltage scalling is one of the more effective and widely used methods for power-aware computing. Here is a DVS approach that uses dynamic detection and correction of circuit timing errors to tune processor supply voltage and eliminate the need for voltage margins.

UR - http://www.scopus.com/inward/record.url?scp=15044339297&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=15044339297&partnerID=8YFLogxK

U2 - 10.1109/MM.2004.85

DO - 10.1109/MM.2004.85

M3 - Article

AN - SCOPUS:15044339297

SN - 0272-1732

VL - 24

SP - 10

EP - 20

JO - IEEE Micro

JF - IEEE Micro

IS - 6

ER -

Razor: Circuit-level correction of timing errors for low-power operation

Abstract

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