Razor: A low-power pipeline based on circuit-level timing speculation

D. Ernst, Nam Sung Kim, S. Das, S. Pant, R. Rao, Toan Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, T. Mudge

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for power-aware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst-case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst-case combination of different variabilities is very rare. In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. The key idea of Razor is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. A prototype Razor pipeline was designed in a 0.18 μm technology and was analyzed. Razor energy overhead during normal operation is limited to 3.1%. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%).

Original languageEnglish (US)
Title of host publicationProceedings - 36th International Symposium on Microarchitecture, MICRO 2003
PublisherIEEE Computer Society
Pages7-18
Number of pages12
ISBN (Electronic)076952043X
DOIs
StatePublished - 2003
Externally publishedYes
Event36th International Symposium on Microarchitecture, MICRO 2003 - San Diego, United States
Duration: Dec 3 2003Dec 5 2003

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
Volume2003-January
ISSN (Print)1072-4451

Other

Other36th International Symposium on Microarchitecture, MICRO 2003
CountryUnited States
CitySan Diego
Period12/3/0312/5/03

Keywords

  • Clocks
  • Delay
  • Dynamic voltage scaling
  • Error correction
  • Frequency
  • Pipelines
  • Silicon
  • Timing
  • Tuned circuits
  • Voltage control

ASJC Scopus subject areas

  • Hardware and Architecture

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