Rail-to-rail input pipelined ADC incorporating multistage signal mapping

Naga Sasidhar, David Gubbins, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Contribution to journalArticlepeer-review

Abstract

In this brief, a design technique for high-speed pipelined analog-to-digital converters (ADCs) that enables processing rail-to-rail input swing without the use of dual set of reference voltages is proposed. The scheme not only operates on a single set of power supplies but also helps in power reduction in the ADC using a new multistage signal mapping technique aided by asynchronous sub-ADC quantization. To further reduce both power and area, an asynchronous successive approximation register ADC backend is used. To demonstrate the efficacy of the proposed techniques, a 1.2-V 10-bit 125-MS/s ADC is designed in a 90-nm CMOS process, and simulation results are presented.

Original languageEnglish (US)
Article number6287564
Pages (from-to)558-562
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume59
Issue number9
DOIs
StatePublished - 2012
Externally publishedYes

Keywords

  • Analog-to-digital converter (ADC)
  • Operational amplifier (Opamp) sharing
  • data converter
  • high speed
  • low power
  • pipeline
  • successive approximation register (SAR)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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