Qusssssantitative analysis of vector code

Roger Espasa, Mateo Valero, David Padua, Marta Jiménez, Eduard Ayguadé

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we present the results of a detailed simulation study of the execution of vector programs on a single processor of a Convex C3480 machine, using a subset of the Perfect Club benchmarks. We are interested in evaluating several eost/performance tradeoffs that the machine designers m.ade in order to asses which features of the architecture severely limit the performance attainable. We present the detailed usage of the vector functional units and a study of the kinds of resource conflicts that stall the machine. The results obtained show that the resources of the vector architecture are not efficiently used mainly due to the single bus memory architecture. Other severe limitations of the machine turn out to be the lack of chaining between vector loads and vector computations, and the lack of a second general purpose functional unit. We also present some data about the port pressure on the vector register file and tve see that stalls due to port conflicts are relatively high. We also consider the slowdown introduced by spill code and find that the limited number of vector registers also limits performance.

Original languageEnglish (US)
Title of host publicationProceedings - Euromicro Workshop on Parallel and Distributed Processing
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages452-461
Number of pages10
ISBN (Electronic)0818670312, 9780818670312
DOIs
StatePublished - Jan 1 1995
Externally publishedYes
Event1995 Euromicro Workshop on Parallel and Distributed Processing - San Remo, Italy
Duration: Jan 25 1995Jan 27 1995

Publication series

NameProceedings - Euromicro Workshop on Parallel and Distributed Processing

Other

Other1995 Euromicro Workshop on Parallel and Distributed Processing
CountryItaly
CitySan Remo
Period1/25/951/27/95

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

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