QuickRec: Prototyping an intel architecture extension for record and replay of multithreaded programs

Gilles Pokam, Klaus Danne, Cristiano Pereira, Rolf Kassa, Tim Kranich, Shiliang Hu, Justin Gottschlich, Nima Honarmand, Nathan Dautenhahn, Samuel T. King, Josep Torrellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

There has been significant interest in hardware-assisted deterministic Record and Replay (RnR) systems for multithreaded programs on multiprocessors. However, no proposal has implemented this technique in a hardware prototype with full operating system support. Such an implementation is needed to assess RnR practicality. This paper presents QuickRec, the first multicore Intel Architecture (IA) prototype of RnR for multithreaded programs. QuickRec is based on QuickIA, an Intel emulation platform for rapid prototyping of new IA extensions. QuickRec is composed of a Xeon server platform with FPGA-emulated second-generation Pentium cores, and Capo 3, a full software stack for managing the recording hardware from within a modified Linux kernel. This paper's focus is understanding and evaluating the implementation issues of RnR on a real platform. Our effort leads to some lessons learned, as well as to some pointers for future research. We demonstrate that RnR can be implemented efficiently on a real multicore IA system. In particular, we show that the rate of memory log generation is insignificant, and that the recording hardware has negligible performance overhead. However, the software stack incurs an average recording overhead of nearly 13%, which must be reduced to enable always-on use of RnR.

Original languageEnglish (US)
Title of host publicationISCA 2013 - 40th Annual International Symposium on Computer Architecture, Conference Proceedings
Pages643-654
Number of pages12
DOIs
StatePublished - Aug 12 2013
Event40th Annual International Symposium on Computer Architecture, ISCA 2013 - Tel-Aviv, Israel
Duration: Jun 23 2013Jun 27 2013

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

Other40th Annual International Symposium on Computer Architecture, ISCA 2013
CountryIsrael
CityTel-Aviv
Period6/23/136/27/13

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Keywords

  • Deterministic Record and Replay
  • FPGA Prototype
  • Hardware-Software Interface
  • Shared Memory Multiprocessors

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Pokam, G., Danne, K., Pereira, C., Kassa, R., Kranich, T., Hu, S., Gottschlich, J., Honarmand, N., Dautenhahn, N., King, S. T., & Torrellas, J. (2013). QuickRec: Prototyping an intel architecture extension for record and replay of multithreaded programs. In ISCA 2013 - 40th Annual International Symposium on Computer Architecture, Conference Proceedings (pp. 643-654). (Proceedings - International Symposium on Computer Architecture). https://doi.org/10.1145/2485922.2485977