TY - GEN
T1 - QuickRec
T2 - 40th Annual International Symposium on Computer Architecture, ISCA 2013
AU - Pokam, Gilles
AU - Danne, Klaus
AU - Pereira, Cristiano
AU - Kassa, Rolf
AU - Kranich, Tim
AU - Hu, Shiliang
AU - Gottschlich, Justin
AU - Honarmand, Nima
AU - Dautenhahn, Nathan
AU - King, Samuel T.
AU - Torrellas, Josep
N1 - Copyright:
Copyright 2013 Elsevier B.V., All rights reserved.
PY - 2013
Y1 - 2013
N2 - There has been significant interest in hardware-assisted deterministic Record and Replay (RnR) systems for multithreaded programs on multiprocessors. However, no proposal has implemented this technique in a hardware prototype with full operating system support. Such an implementation is needed to assess RnR practicality. This paper presents QuickRec, the first multicore Intel Architecture (IA) prototype of RnR for multithreaded programs. QuickRec is based on QuickIA, an Intel emulation platform for rapid prototyping of new IA extensions. QuickRec is composed of a Xeon server platform with FPGA-emulated second-generation Pentium cores, and Capo 3, a full software stack for managing the recording hardware from within a modified Linux kernel. This paper's focus is understanding and evaluating the implementation issues of RnR on a real platform. Our effort leads to some lessons learned, as well as to some pointers for future research. We demonstrate that RnR can be implemented efficiently on a real multicore IA system. In particular, we show that the rate of memory log generation is insignificant, and that the recording hardware has negligible performance overhead. However, the software stack incurs an average recording overhead of nearly 13%, which must be reduced to enable always-on use of RnR.
AB - There has been significant interest in hardware-assisted deterministic Record and Replay (RnR) systems for multithreaded programs on multiprocessors. However, no proposal has implemented this technique in a hardware prototype with full operating system support. Such an implementation is needed to assess RnR practicality. This paper presents QuickRec, the first multicore Intel Architecture (IA) prototype of RnR for multithreaded programs. QuickRec is based on QuickIA, an Intel emulation platform for rapid prototyping of new IA extensions. QuickRec is composed of a Xeon server platform with FPGA-emulated second-generation Pentium cores, and Capo 3, a full software stack for managing the recording hardware from within a modified Linux kernel. This paper's focus is understanding and evaluating the implementation issues of RnR on a real platform. Our effort leads to some lessons learned, as well as to some pointers for future research. We demonstrate that RnR can be implemented efficiently on a real multicore IA system. In particular, we show that the rate of memory log generation is insignificant, and that the recording hardware has negligible performance overhead. However, the software stack incurs an average recording overhead of nearly 13%, which must be reduced to enable always-on use of RnR.
KW - Deterministic Record and Replay
KW - FPGA Prototype
KW - Hardware-Software Interface
KW - Shared Memory Multiprocessors
UR - http://www.scopus.com/inward/record.url?scp=84881150400&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84881150400&partnerID=8YFLogxK
U2 - 10.1145/2485922.2485977
DO - 10.1145/2485922.2485977
M3 - Conference contribution
AN - SCOPUS:84881150400
SN - 9781450320795
T3 - Proceedings - International Symposium on Computer Architecture
SP - 643
EP - 654
BT - ISCA 2013 - 40th Annual International Symposium on Computer Architecture, Conference Proceedings
Y2 - 23 June 2013 through 27 June 2013
ER -