Quaternary Logic Circuits in 2-μm CMOS Technology

Naresh R. Shanbhag, Dipankar Nagchoudhuri, Raymond E. Siferd, Gangaikond S. Visweswaran

Research output: Contribution to journalArticlepeer-review

Abstract

Novel quaternary logic circuits, designed in 2-μm CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-to-binary decoder, and the quaternary register designs are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra, has been designed and fabricated. The prototype chip occupies an area of 4.84 mm2, is timed with a 2.2-MHz clock, and consumes 93 mW of power.

Original languageEnglish (US)
Pages (from-to)790-799
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume25
Issue number3
DOIs
StatePublished - Jun 1990
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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