Quantitative analysis of processor - programmable logic interface

Sriram Rajamani, Pramod Viswanath

Research output: Contribution to journalConference article

Abstract

The addition of programmable logic to RISC machines has the potential of exploiting the inherent parallelism of hardware to speedup an application. In this paper, we study the effect of adding a programmable accelerator to DLX, a RISC prototype. We build this model and parameterize the communication overhead between the processor and programmable unit and logic/routing delays inside the programmable unit. We use simulation to evaluate the performance of this model, parameterized by communication overhead and logic delays, by comparing it with the baseline DLX architecture on some sample problems. Our methodology is useful in studying the relative importance of the parameters and in projecting the performance of the system, if the programmable logic were to be implemented inside the processor.

Original languageEnglish (US)
Pages (from-to)226-234
Number of pages9
JournalIEEE Symposium on FPGAs for Custom Computing Machines, Proceedings
StatePublished - Dec 1 1996
Externally publishedYes
EventProceedings of the 1996 IEEE Symposium on FPGAs for Custom Computing Machines - Napa Valley, CA, USA
Duration: Apr 17 1996Apr 19 1996

Fingerprint

Reduced instruction set computing
Interfaces (computer)
Program processors
Communication
Chemical analysis
Particle accelerators
Hardware

ASJC Scopus subject areas

  • Computer Science(all)
  • Engineering(all)

Cite this

Quantitative analysis of processor - programmable logic interface. / Rajamani, Sriram; Viswanath, Pramod.

In: IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings, 01.12.1996, p. 226-234.

Research output: Contribution to journalConference article

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