Pulsar: Non-blocking packet switching with shift-register rings

Gary J. Muralwni, Roy H. Campbell, Michael Faiman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper discusses the design of a switch for high-speed computer networking at gigabit rates. We present the Pulsar switch, a non-blocking design based on a high-spin-rate, port-dedicated, word-parallel, shift-register ring. Several design alternatives address the problem of Head-Of-Line blocking. In contrast to Batcher-Banyan switches, access to the ring is asynchronous which facilitates low delay and arbitrary packet length. The switch can support ATM cells simultaneously with packets sized for applications such as single characters, memory words, disk blocks, memory pages, or video images. Pulsar can be used as a high-throughput computer backplane replacement. The design can be implemented with existing high-speed circuit technology.

Original languageEnglish (US)
Title of host publicationProceedings of the ACM Symposium on Communications Architectures and Protocols, SIGCOMM 1990
PublisherAssociation for Computing Machinery, Inc
Pages145-155
Number of pages11
ISBN (Electronic)0897914058, 9780897914055
DOIs
StatePublished - Aug 1 1990
Event1990 ACM Symposium on Communications Architectures and Protocols, SIGCOMM 1990 - Philadelphia, United States
Duration: Sep 26 1990Sep 28 1990

Publication series

NameProceedings of the ACM Symposium on Communications Architectures and Protocols, SIGCOMM 1990

Other

Other1990 ACM Symposium on Communications Architectures and Protocols, SIGCOMM 1990
CountryUnited States
CityPhiladelphia
Period9/26/909/28/90

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Computer Networks and Communications

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