TY - GEN
T1 - PTAH
T2 - 4th International Parallel Architectures and Languages Europe Conference, PARLE 1992
AU - Cappello, Franck
AU - Béchennec, Jean Luc
AU - Giavitto, Jean Louis
N1 - Funding Information:
The PTAH Project is developed within the "Computer Architecture and VLSI Design" Research Group at LRI. The authors do thanks the other members of this group: C. Germain for his outstanding contribution, J.-P. Sansonnet and D. Etiemble for many helpful comments and support and F. Delaplace for fruitful discussions. This work is partially supported by the french national research program on New Computer Architectures (PRC-ANM) and by DRET under grant #89342320047050/.
Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 1992.
PY - 1992
Y1 - 1992
N2 - This paper proposes a new architectural design for high performance parallel computers: the one-cycle machine. In such a computer the memory access, network access, instruction sequencing, data computation take the same duration: one clock cycle. We first consider the communication network efficiency as the main critical resource. We show that the adaptation of the network performance to the processing element power is more important than the CPU power in itself with respect to the global processing effectiveness. Two guidelines are derived from our analysis and conduct to the design of PTAH. Two simple examples are used to illustrate the interest of PTAH for the execution of numeric applications. Finally, some hardware features are proposed for a PTAH implementation being able to reach the TeraFLOPS.
AB - This paper proposes a new architectural design for high performance parallel computers: the one-cycle machine. In such a computer the memory access, network access, instruction sequencing, data computation take the same duration: one clock cycle. We first consider the communication network efficiency as the main critical resource. We show that the adaptation of the network performance to the processing element power is more important than the CPU power in itself with respect to the global processing effectiveness. Two guidelines are derived from our analysis and conduct to the design of PTAH. Two simple examples are used to illustrate the interest of PTAH for the execution of numeric applications. Finally, some hardware features are proposed for a PTAH implementation being able to reach the TeraFLOPS.
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U2 - 10.1007/3-540-55599-4_82
DO - 10.1007/3-540-55599-4_82
M3 - Conference contribution
AN - SCOPUS:84955566932
SN - 9783540555995
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 81
EP - 96
BT - PARLE 1992 Parallel Architectures and Languages Europe - 4th International PARLE Conference, Proceedings
A2 - Etiemble, Daniel
A2 - Syre, Jean-Claude
PB - Springer
Y2 - 15 June 1992 through 18 June 1992
ER -