Prototyping architectural support for program rollback using FPGAs

Radu Teodorescu, Josep Torrellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a processor and memory-hierarchy prototype based on FPGAs that provides hardware support for program rollback. We use this prototype to demonstrate how compiler- or user-controlled speculative execution can help in debugging production codes. The system is based on a synthesizable VHDL implementation of a 32-bit processor compliant with the SPARC V8 architecture. We conduct experiments on applications with real bugs. The applications run on top of a version of Linux ported to this hardware. Our experiments show that our system is able to successfully execute the buggy code sections speculatively. This allows the thorough characterization of the faulty code through repeated rollback and re-execution. Moreover, the hardware extensions we made to the baseline system increase the hardware resource requirements by less than 4.5%.

Original languageEnglish (US)
Title of host publicationProceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005
Pages23-32
Number of pages10
DOIs
StatePublished - Dec 1 2005
Event13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005 - Napa, CA, United States
Duration: Apr 18 2005Apr 20 2005

Publication series

NameProceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005
Volume2005

Other

Other13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005
Country/TerritoryUnited States
CityNapa, CA
Period4/18/054/20/05

ASJC Scopus subject areas

  • Engineering(all)

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