PROMISE: An end-to-End design of a programmable mixed-Signal accelerator for Machine-Learning algorithms

Prakalp Srivastava, Mingu Kang, Sujan K. Gonugondla, Sungmin Lim, Jungwook Choi, Vikram Adve, Nam Sung Kim, Naresh Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Analog/mixed-signal Machine learning (ML) accelerators exploit the unique computing capability of analog/mixed-signal circuits and inherent error tolerance of ML algorithms to obtain higher energy efficiencies than digital ML accelerators. Unfortunately, these analog/mixed-signal ML accelerators lack programmability, and even instruction set interfaces, to support diverse ML algorithms or to enable essential software control over the energy-vs-accuracy tradeoffs. We propose PROMISE, the first end-to-end design of a PROgrammable MIxed-Signal accElerator from Instruction Set Architecture (ISA) to high-level language compiler for acceleration of diverse ML algorithms. We first identify prevalent operations in widely-used ML algorithms and key constraints in supporting these operations for a programmable mixed-signal accelerator. Second, based on that analysis, we propose an ISA with a PROMISE architecture built with silicon-validated components for mixed-signal operations. Third, we develop a compiler that can take a ML algorithm described in a high-level programming language (Julia) and generate PROMISE code, with an IR design that is both language-neutral and abstracts away unnecessary hardware details. Fourth, we show how the compiler can map an application-level error tolerance specification for neural network applications down to low-level hardware parameters (swing voltages for each application Task) to minimize energy consumption. Our experiments show that PROMISE can accelerate diverse ML algorithms with energy efficiency competitive even with fixed-function digital ASICs for specific ML algorithms, and the compiler optimization achieves significant additional energy savings even for only 1% extra errors.

Original languageEnglish (US)
Title of host publicationProceedings - 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture, ISCA 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages43-56
Number of pages14
ISBN (Electronic)9781538659847
DOIs
StatePublished - Jul 19 2018
Event45th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2018 - Los Angeles, United States
Duration: Jun 2 2018Jun 6 2018

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

Other45th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2018
Country/TerritoryUnited States
CityLos Angeles
Period6/2/186/6/18

Keywords

  • Analog ISA
  • Deep in-memory computing
  • Programmable Machine learning accelerator

ASJC Scopus subject areas

  • Hardware and Architecture

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