Projecting lifetime of deep submicron MOSFETs

Erhong Li; Elyse Rosenbaum; Jiang Tao; Peng Fang

doi:10.1109/16.915682

Projecting lifetime of deep submicron MOSFETs

Erhong Li, Elyse Rosenbaum, Jiang Tao, Peng Fang

Research output: Contribution to journal › Article › peer-review

Abstract

A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-μm and a 0.1-μm technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I _b,peak is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in Deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons.

Original language	English (US)
Pages (from-to)	671-678
Number of pages	8
Journal	IEEE Transactions on Electron Devices
Volume	48
Issue number	4
DOIs	https://doi.org/10.1109/16.915682
State	Published - Apr 2001

Keywords

Hot-carrier-induced degradation
Worst case stress condition

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Online availability

10.1109/16.915682

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title = "Projecting lifetime of deep submicron MOSFETs",

abstract = "A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-μm and a 0.1-μm technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I b,peak is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in Deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons.",

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note = "Funding Information: Manuscript received February 6, 2000; revised June 26, 2000. This work was supported by the Semiconductor Research Corporation under the AMD Research Customization Program. The review of this paper was arranged by Editor Guido Groeseneken E. Li was with the Electrical and Computer Engineering Department, University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA. He is now with LSI Logic, Milpitas CA 95035 USA. E. Rosenbaum is with the Electrical and Computer Engineering Department, University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA. J. Tao and P. Fang are with Advanced Micro Devices, Sunnyvale, CA 94088 USA. Publisher Item Identifier S 0018-9383(01)02344-9.",

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AU - Rosenbaum, Elyse

AU - Tao, Jiang

AU - Fang, Peng

N1 - Funding Information: Manuscript received February 6, 2000; revised June 26, 2000. This work was supported by the Semiconductor Research Corporation under the AMD Research Customization Program. The review of this paper was arranged by Editor Guido Groeseneken E. Li was with the Electrical and Computer Engineering Department, University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA. He is now with LSI Logic, Milpitas CA 95035 USA. E. Rosenbaum is with the Electrical and Computer Engineering Department, University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA. J. Tao and P. Fang are with Advanced Micro Devices, Sunnyvale, CA 94088 USA. Publisher Item Identifier S 0018-9383(01)02344-9.

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N2 - A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-μm and a 0.1-μm technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I b,peak is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in Deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons.

AB - A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-μm and a 0.1-μm technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I b,peak is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in Deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons.

KW - Hot-carrier-induced degradation

KW - Worst case stress condition

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Projecting lifetime of deep submicron MOSFETs

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Keywords

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