Programmable spatiotemporal image processor chip

A 16×16 pixel pseudo general-purpose vision chip for spatiotemporal focal-plane processing is presented. The convolution of the image with programmable kernels are realized with area-efficient and real-time circuits. The chip's architecture allows the photoreceptor cells to be small and densely packed by performing all analog computations on the read-out, away from the array. The size, configuration and coefficients of the kernels can be varied on the fly. In addition to the raw intensity image, the chip outputs four processed images in parallel. The convolution is implemented with a digitally programmable analog processor, resulting in very low power consumption at high computation rates.