Programmable spatial processing imager chip

V. Gruev, R. Etienne-Cummings

Research output: Contribution to journalArticlepeer-review

Abstract

The authors present an architectural overview and results from an image processor chip for realising steerable spatial filtering at the focal plane. Convolutions of the image with multiple programmable kernels are realised with area-efficient, real-time circuits. In addition to the raw intensity image, the chip outputs four processed images in parallel. The convolutions are implemented with digitally programmable analogue processors. The chip performs 5.7 GOPS/mW while outputting four processed images in parallel.

Original languageEnglish (US)
Pages (from-to)688-690
Number of pages3
JournalElectronics Letters
Volume37
Issue number11
DOIs
StatePublished - May 24 2001
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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