Profile-driven instruction level parallel scheduling with application to super blocks

C. Chekuri, R. Johnson, R. Motwani, B. Natarajan, B. R. Rau, M. Schlansker

Research output: Contribution to journalConference articlepeer-review

Abstract

A general paradigm for converting any profile-insensitive list to a profile-sensitive scheduler is proposed. This technique is developed via a theoretical analysis of a simplified abstract model of the general problem of profile-driven scheduling over any cyclic code region, yielding a scoring measure for ranking branch instructions. The ranking digests the profile information and has the useful property that scheduling with respect to rank is probably good for minimizing the expected completion time of the region, within the limits of abstraction. While the ranking scheme is computationally intractable in the most general case, this is practicable for super blocks.

Original languageEnglish (US)
Pages (from-to)58-67
Number of pages10
JournalProceedings of the Annual International Symposium on Microarchitecture
StatePublished - Dec 1 1996
Externally publishedYes
EventProceedings of the 1996 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-29 - Paris, Fr
Duration: Dec 2 1996Dec 4 1996

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

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