Process, temperature, and supply-noise tolerant 45nm dense cache arrays with Diffusion-Notch-Free (DNF) 6T SRAM cells and dynamic multi-Vcc circuits

Muhammad Khellah, Nam Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De

Research output: Contribution to journalArticle

Abstract

This paper addresses the stability problem of diffusion-notch-free (DNF) SRAM cells used in dense last level caches (LLC). A DNF cell eliminates lithographic induced variations due to nMOS diffusion notches used in conventional 6T SRAM cells. However, it also results in reduced overall cell stability.We describe a new WL under-drive (WLUD) circuit that enables a read stable DNF cell with all minimally sized devices (called M-cell). The proposed WLUD circuit is both PT and supply noise tolerant. Write stability is maintained at low voltage thanks to a V CC dynamic voltage collapse (DVC) scheme that trades large dynamic cell retention margin for improving write stability. Another DNF cell, called P-cell, with pMOS pass device and charged high bit-lines is also presented. This cell is inherently read ratio-ed and extra read margin can be obtained through upsizing the nMOS PD without creating a notch as in conventional cell. A V SS DVC circuit is used along the P-cell to recover write stability. Two SRAM macros in 45 nm were fabricated to experiment with the proposed schemes. Both simulation and measurement results confirm that ̃20% WLUD along with proper V CC DVC enables a stable M-cell across a wide voltage range. A low voltage operating window for the P-cell also exists by appropriately selecting pMOS strength, nMOS pull-down size, and V SS DVC.

Original languageEnglish (US)
Article number4804978
Pages (from-to)1199-1208
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number4
DOIs
StatePublished - Apr 1 2009

Keywords

  • SRAM
  • Stability
  • Supply noise
  • V
  • Variation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Process, temperature, and supply-noise tolerant 45nm dense cache arrays with Diffusion-Notch-Free (DNF) 6T SRAM cells and dynamic multi-Vcc circuits'. Together they form a unique fingerprint.

  • Cite this

    Khellah, M., Kim, N. S., Ye, Y., Somasekhar, D., Karnik, T., Borkar, N., Pandya, G., Hamzaoglu, F., Coan, T., Wang, Y., Zhang, K., Webb, C., & De, V. (2009). Process, temperature, and supply-noise tolerant 45nm dense cache arrays with Diffusion-Notch-Free (DNF) 6T SRAM cells and dynamic multi-Vcc circuits. IEEE Journal of Solid-State Circuits, 44(4), 1199-1208. [4804978]. https://doi.org/10.1109/JSSC.2009.2014015