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Process induced stresses in cavity SOI wafers
O. Elkhatib
, J. Makinen
, M. Palokangas
, T. W. Lin
,
H. T. Johnson
, G. P. Horn
Mechanical Science and Engineering
Materials Science and Engineering
Materials Research Lab
National Center for Supercomputing Applications (NCSA)
Research output
:
Chapter in Book/Report/Conference proceeding
›
Conference contribution
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Keyphrases
SOI Wafer
100%
Residual Stress
100%
Cavity-SOI
100%
Process-induced Stress
100%
Resonator
50%
Bonded Wafer
50%
Wafer
50%
Oxidation Mechanism
50%
Tensile Stress
50%
Residual Stress State
50%
MEMS-based
50%
Silicon-on-insulator Wafer
50%
High-temperature Annealing
50%
Buried Cavities
50%
Cavity Geometry
50%
Reliability Issues
50%
Etched Silicon
50%
Double Gate
50%
Stress Concentration
50%
Wafer Thinning
50%
Infrared Polariscope
50%
Silicon Cavity
50%
After High Temperature
50%
MOS Devices
50%
Recent Applications
50%
Material Science
Residual Stress
100%
Silicon
66%
Microelectromechanical System
33%
Resonator
33%
Annealing
33%
Stress Concentration
33%
Ultimate Tensile Strength
33%