PROBLEM SIZE, PARALLEL ARCHITECTURE, AND OPTIMAL SPEEDUP.

David M. Nicol, Frank H. Willard

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The authors examine the numerical solution of an elliptic partial differential equation in order to study the relationship between problem size and architecture. The equation's domain is discretized into n**2 grid points which are divided into partitions and mapped onto the individual processor memories. The relationships among grid size, stencil type, partitioning strategy, processor execution time, and communication network type are quantified. The authors thus determine the optimal number of processors to assign to the solution (and hence the optimal speedup), and identify (1) the smallest grid which fully benefits from using all available processors, (2) the leverage on performance given by increasing processor speed or communication network speed, and (3) the suitability of various architectures for large numerical problems.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Parallel Processing
EditorsSartaj K. Sahni
PublisherPennsylvania State Univ Press
Pages347-354
Number of pages8
ISBN (Print)0271006080
StatePublished - Dec 1 1987
Externally publishedYes
EventProc Int Conf Parallel Process 1987 - Universal Park, PA, USA
Duration: Aug 17 1987Aug 21 1987

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918

Other

OtherProc Int Conf Parallel Process 1987
CityUniversal Park, PA, USA
Period8/17/878/21/87

ASJC Scopus subject areas

  • Hardware and Architecture

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  • Cite this

    Nicol, D. M., & Willard, F. H. (1987). PROBLEM SIZE, PARALLEL ARCHITECTURE, AND OPTIMAL SPEEDUP. In S. K. Sahni (Ed.), Proceedings of the International Conference on Parallel Processing (pp. 347-354). (Proceedings of the International Conference on Parallel Processing). Pennsylvania State Univ Press.