Probabilistic-physics-of-failure/short-time-test approach to reliability assurance for high-performance chips: Models for deep-submicron transistors and optical interconnects

A. Haggag, W. McMahon, K. Hess, K. Cheng, J. Lee, Joseph W Lyding

Research output: Contribution to conferencePaper

Abstract

This paper deviates from strictly empirical chip reliability approaches and uses instead a chip reliability methodology based on probabilistic-physics-of-failure (PPoF) principles. We derive the failure-time distribution of both deep-submicron transistors and optical interconnects owing to the presence of a common defect activation energy distribution. We show how short-time device degradation can be used to extract the tails of the semi-symmetric failure-time distribution (important for long-term reliability qualification). Applying novel reliability qualification rules based on this failure-time distribution, `latent failures' can then be avoided through design changes for reliability.

Original languageEnglish (US)
Pages179-182
Number of pages4
StatePublished - Dec 1 2000
Event2000 IEEE International Integrated Reliability Workshop - Lake Tahoe, CA, USA
Duration: Oct 23 2000Oct 26 2000

Other

Other2000 IEEE International Integrated Reliability Workshop
CityLake Tahoe, CA, USA
Period10/23/0010/26/00

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

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  • Cite this

    Haggag, A., McMahon, W., Hess, K., Cheng, K., Lee, J., & Lyding, J. W. (2000). Probabilistic-physics-of-failure/short-time-test approach to reliability assurance for high-performance chips: Models for deep-submicron transistors and optical interconnects. 179-182. Paper presented at 2000 IEEE International Integrated Reliability Workshop, Lake Tahoe, CA, USA, .