Probabilistic counter updates for predictor hysteresis and stratification

Nicholas Riley, Craig Zilles

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Hardware counters are a fundamental building block of modern high-performance processors. This paper explores two applications of probabilistic counter updates, in which the output of a pseudo-random number generator decides whether to perform a counter increment or decrement. First, we discuss a probabilistic implementation of counter hysteresis, whereby previously proposed branch confidence and criticality predictors can be reduced in size by factors of 2 and 3, respectively, with negligible impact on performance. Second, we build a frequency stratifier by making increment and decrement probabilities functions of the current counter value. The stratifier enables a 4-bit counter to classify an instruction's Likelihood of Criticality with sufficient accuracy to closely approximate the performance of an unbounded precision classifier. Because probabilistic updates are both simple and effective, we believe these ideas hold great promise for immediate use by industry, perhaps enabling the use of structures such as branch confidence predictors which may have previously been viewed as too expensive given their functionality.

Original languageEnglish (US)
Title of host publicationProceedings - Twelfth International Symposium on High-Performance Computer Architecture, 2006
Pages111-121
Number of pages11
DOIs
StatePublished - Sep 26 2006
EventTwelfth International Symposium on High-Performance Computer Architecture, 2006 - Austin, TX, United States
Duration: Feb 11 2006Feb 15 2006

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
Volume2006
ISSN (Print)1530-0897

Other

OtherTwelfth International Symposium on High-Performance Computer Architecture, 2006
CountryUnited States
CityAustin, TX
Period2/11/062/15/06

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Riley, N., & Zilles, C. (2006). Probabilistic counter updates for predictor hysteresis and stratification. In Proceedings - Twelfth International Symposium on High-Performance Computer Architecture, 2006 (pp. 111-121). [1598118] (Proceedings - International Symposium on High-Performance Computer Architecture; Vol. 2006). https://doi.org/10.1109/HPCA.2006.1598118