Probabilistic counter updates for predictor hysteresis and bias

Nicholas Riley, Craig Zilles

Research output: Contribution to journalArticlepeer-review


Hardware predictor designers have incorporated , hysteresis and/or bias to achieve desired behavior by increasing the number of bits per counter. Some resulting proposed predictor designs are currently impractical because their counter tables are too large. We describe a method for dramatically reducing the amount of storage required for a predictor's counter table with minimal impact on prediction accuracy. Probabilistic updates to counter state are implemented using a hardware pseudo-random number generator to increment or decrement counters a fraction of the time, meaning fewer counter bits are required. We demonstrate the effectiveness of probabilistic updates in the context of Fields et al.'s critical path predictor, which employs a biased 6-bit counter. Averaged across the SPEC CINT2000 benchmarks, our 2-bit and 3-bit probabilistic counters closely approximate a 6-bit deterministic one (achieving speedups of 7.75% and 7.91% compared to 7.94%) when used for criticality-based scheduling in a clustered machine. Performance degrades gracefully, enabling even a 1-bit probabilistic counter to outper-form the best 3-bit deterministic counter we found.

Original languageEnglish (US)
Pages (from-to)18-21
Number of pages4
JournalIEEE Computer Architecture Letters
Issue number1
StatePublished - Jan 2006

ASJC Scopus subject areas

  • Hardware and Architecture


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