A computer processor which speculatively issues prefetch addresses for indirect as well as linear memory traversals after entering an armed state. A particular embodiment of the invention includes a central processing unit connected to an external memory through an interface. A cache memory, preferably integrated onto a processor chip with the central processing unit, is connected to both the central processing unit and the interface. A prefetch device is also preferably integrated onto the chip and selectively issues prefetch addresses after entering an armed state induced by recognized patterns in memory operand addresses of load instructions executed by the central processing unit. The prefetch device includes a recurrence recognition unit and a prefetch unit. When either the linear or indirect armed states are entered, the recurrence recognition unit will direct the prefetch unit to issue prefetch addresses according to a calculated linear or indirect stride. Linear memory traversals may be predicted according to the linear stride, while indirect memory traversals may be predicted according to the indirect stride.
|Original language||English (US)|
|U.S. patent number||5694568|
|State||Published - Dec 2 1997|