Power domain crossing circuits, also known as internal I/O's, are susceptible to gate oxide damage during charged device model (CDM) events. Circuit-level simulations of internal I/O circuits along with elements representing the package, electro-static discharge (ESD) circuits and the substrate, elucidate the roles of the package, power clamp placement, back-to-back diode placement and the decoupling capacitors in determining the amount of stress at the internal I/O circuits. This paper presents an internal I/O model that can be used for CDM simulations. The effects of power and ground bus resistance, substrate resistivity, decoupling capacitance, local ESD clamp at the gate of the receiver and the presence of local back-to-back diodes are investigated. The paper further contains design recommendations for preventing CDM failures in the internal I/O circuits.