Abstract
In this paper we investigate and develop models for Partially-Depleted SOI (PD-SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (It2) for salicided PD-SOI MOSFETs with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under HBM-ESD stress pulses. Furthermore, It2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device have been shown to achieve HBM-ESD protection levels of ±3.75 kV.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 356-365 |
| Number of pages | 10 |
| Journal | Electrical Overstress/Electrostatic Discharge Symposium Proceedings |
| State | Published - 1997 |
| Event | Proceedings of the 1997 Electrical Overstress/Electrostatic Discharge Symposium - Santa Clara, CA, USA Duration: Sep 23 1997 → Sep 25 1997 |
ASJC Scopus subject areas
- Condensed Matter Physics