Predicting performance on SMPs. A case study: The SGI Power Challenge

Nancy M. Amato, Jack Perdue, Andrea Pietracaprina, Geppino Pucci, Mark Mathis

Research output: Contribution to journalArticlepeer-review

Abstract

We study the issue of performance prediction on the SGI-Power Challenge, a typical SMP. On such a platform, the cost of memory accesses depends on their locality and on contention among processors. By running a carefully designed suite of microbenchmarks, we provide quantitative evidence that memory hierarchy effects impact performance far more substantially than other phenomena related to contention. We also fit three cost functions based on variants of the BSP model, which do not account for the hierarchy, and a newly defined function F expressed in terms of hardware counters, which captures both memory hierarchy and contention effects. We test the accuracy of all the functions on both synthetic and application benchmarks showing that, unlike the other functions, F achieves an excellent level of accuracy in all cases. Although hardware counters are only available at run-time, we give evidence that function F can still be employed as a prediction tool by extrapolating values of the counters from pilot runs on small input sizes.

Original languageEnglish (US)
Pages (from-to)729-737
Number of pages9
JournalProceedings of the International Parallel Processing Symposium, IPPS
StatePublished - Jan 1 2000
Externally publishedYes

ASJC Scopus subject areas

  • Hardware and Architecture

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