Predicting memory-access cost based on data-access patterns

Surendra Byna, Xian He Sun, William D Gropp, Rajeev Thakur

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Improving memory performance at software level is more effective in reducing the rapidly expanding gap between processor and memory performance. Loop transformations (e.g. loop unrolling, loop tiling) and array restructuring optimizations improve the memory performance by increasing the locality of memory accesses. To find the best optimization parameters at runtime, we need a fast and simple analytical model to predict the memory access cost. Most of the existing models are complex and impractical to be integrated in the runtime tuning systems. In this paper, we propose a simple, fast and reasonably accurate model that is capable of predicting the memory access cost based on a wide range of data access patterns that appear in many scientific applications.

Original languageEnglish (US)
Title of host publication2004 IEEE International Conference on Cluster Computing, ICCC 2004
Pages327-336
Number of pages10
DOIs
StatePublished - 2004
Event2004 IEEE International Conference on Cluster Computing, ICCC 2004 - San Diego, CA, United States
Duration: Sep 20 2004Sep 23 2004

Publication series

NameProceedings - IEEE International Conference on Cluster Computing, ICCC
ISSN (Print)1552-5244

Other

Other2004 IEEE International Conference on Cluster Computing, ICCC 2004
Country/TerritoryUnited States
CitySan Diego, CA
Period9/20/049/23/04

ASJC Scopus subject areas

  • Engineering(all)

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