Practical methodology for the extraction of SEED models

Collin Reiman, Nicholas Thomson, Yang Xiu, Robert Mertens, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A custom test board facilitates TLP characterization of the external pins of an integrated circuit. Models extracted from the data are used to simulate the pin-level response of the IC to an IEC 61000-4-2 discharge. ESD gun zaps are applied to the test board; simulated and measured waveforms are compared.

Original languageEnglish (US)
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2015
PublisherESD Association
ISBN (Electronic)1585372722, 9781585372737
StatePublished - Oct 30 2015
Event37th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2015 - Reno, United States
Duration: Sep 27 2015Oct 2 2015

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
Volume2015-October
ISSN (Print)0739-5159

Other

Other37th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2015
CountryUnited States
CityReno
Period9/27/1510/2/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Reiman, C., Thomson, N., Xiu, Y., Mertens, R., & Rosenbaum, E. (2015). Practical methodology for the extraction of SEED models. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2015 (Electrical Overstress/Electrostatic Discharge Symposium Proceedings; Vol. 2015-October). ESD Association.