Practical Challenges in Supporting Function in Memory

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The performance of computer systems is often limited by the bandwidth of their memory channels, but further increasing the bandwidth is challenging under the stringent pin and power constraints of packages. To further increase performance under these constraints, various processing-in-memory (or function-in-memory) architectures, which tightly integrate processing functions with DRAM devices using 3D/2.5D-stacking technology, have been proposed. However, they have not been successfully commercialized by the industry yet because of various technical and practical challenges. In this article for the plenary talk, I will briefly discuss what challenges have been overlooked by researchers to shed light on successful commercialization and wide adoption of processing-in-memory architecture.

Original languageEnglish (US)
Title of host publication2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages9-12
Number of pages4
ISBN (Electronic)9781538664124
DOIs
StatePublished - Dec 14 2018
Externally publishedYes
Event2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, Taiwan, Province of China
Duration: Nov 5 2018Nov 7 2018

Publication series

Name2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

Conference

Conference2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
CountryTaiwan, Province of China
CityTainan
Period11/5/1811/7/18

Keywords

  • 3D Stacking
  • DRAM
  • Function in Memory
  • Processing in Memory

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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