Power savings in processors

John Sartori; Hari Cherupalli; Rakesh Kumar

Power savings in processors

John Sartori (Inventor)
, Hari Cherupalli (Inventor)
, Rakesh Kumar (Inventor)

Research output: Patent

Abstract

A method includes generating gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application. The method includes performing a constrained timing analysis on the processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the processor.

Original language	English (US)
U.S. patent number	10866630
Filing date	6/12/18
State	Published - Dec 15 2020

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title = "Power savings in processors",

abstract = "A method includes generating gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application. The method includes performing a constrained timing analysis on the processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the processor.",

author = "John Sartori and Hari Cherupalli and Rakesh Kumar",

year = "2020",

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day = "15",

language = "English (US)",

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AU - Cherupalli, Hari

AU - Kumar, Rakesh

PY - 2020/12/15

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N2 - A method includes generating gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application. The method includes performing a constrained timing analysis on the processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the processor.

AB - A method includes generating gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application. The method includes performing a constrained timing analysis on the processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the processor.

M3 - Patent

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Y2 - 2018/06/12

ER -

Power savings in processors

Abstract

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