Abstract
A method includes generating gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application. The method includes performing a constrained timing analysis on the processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the processor.
| Original language | English (US) |
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| U.S. patent number | 11301030 |
| Filing date | 10/27/20 |
| State | Published - Apr 12 2022 |