Power savings in processors

John Sartori (Inventor), Hari Cherupalli (Inventor), Rakesh Kumar (Inventor)

Research output: Patent


A method includes generating gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application. The method includes performing a constrained timing analysis on the processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the processor.
Original languageEnglish (US)
U.S. patent number10866630
StatePublished - Dec 15 2020


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