Power-performance trade-offs in nanometer-scale multi-level caches considering total leakage

Robert Bai, Nam Sung Kim, Tae Ho Kgil, Dennis Sylvester, Trevor Mudge

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we investigate the impact of T ox and V th, on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a single level cache and then extend this to two level cache systems. In addition to leakage, our studies also account for the dynamic power expended as a result of cache misses. Our results show that one can often reduce overall power by increasing the size of the L2 cache if we only allow one pair of V th/T ox in L2. However, if we allow the memory cells and the peripherals to have their own V th,'s and T ox's, we show that a two-level cache system with smaller L2's will yield less total leakage. We further show that two V th's and two T ox's are sufficient to get close to an optimal solution, and that V th, is generally a better design knob than T ox for leakage optimization, thus it is better to restrict the number of T ox'S rather than V th,'s if cost is a concern.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE '05
Pages650-651
Number of pages2
DOIs
StatePublished - 2005
Externally publishedYes
EventDesign, Automation and Test in Europe, DATE '05 - Munich, Germany
Duration: Mar 7 2005Mar 11 2005

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE '05
VolumeI
ISSN (Print)1530-1591

Other

OtherDesign, Automation and Test in Europe, DATE '05
Country/TerritoryGermany
CityMunich
Period3/7/053/11/05

ASJC Scopus subject areas

  • Engineering(all)

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