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Power balanced pipelines
John Sartori
, Ben Ahrens
,
Rakesh Kumar
Electrical and Computer Engineering
Information Trust Institute
Coordinated Science Lab
Siebel School of Computing and Data Science
Research output
:
Chapter in Book/Report/Conference proceeding
›
Conference contribution
Overview
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Keyphrases
Microarchitecture
100%
Power Balance
100%
Pipeline Stages
66%
Power Reduction
33%
Processor Pipeline
33%
Power Optimized
33%
Time Constraints
16%
Low Power
16%
Design Objectives
16%
Concept of Power
16%
Significant Energy
16%
Power Consumption
16%
Dynamic Method
16%
Energy Efficiency
16%
Power Saving
16%
Frequency Performance
16%
Processor Power
16%
Concept Use
16%
Static Cycle
16%
Pipelined Processors
16%
Power Disparities
16%
Low Operating Frequency
16%
Processor Frequency
16%
Primary Design
16%
Reduced Voltage
16%
Computer Science
Pipeline Stage
100%
Pipeline Processor
50%
Microarchitecture
25%
Power Consumption
25%
Timing Constraint
25%
Pipelined Processor
25%
Throughput Processor
25%
Design Objective
25%
Operating Frequency
25%